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The Gnd connected to the NI input of my bloc amplifier is considered as a reference equals to 0 V. So, I think that I should to connect it as a signal using I/O APRIOP PAD!
Hi everyone,
To have a symmetrical supply power of my design, I have put the VDDA to +1.65 (techno AMC c35 3.3V) and VSSA to -1.65V. And I have several blocs that have one node to GND=0V (for example the positive input of the integrator amp-op). As I have finished the circuit layout, I want to...
, it is a thread on researchgate, there is one solution of implementing back_to_back_silicon_diodes_in_the_negative_feeback_path_of_an_op-amp_in_CMOS, you can adjust it to the bridge
I am agree with you, i.e, as the substrate is always connected to the lowest supply voltage (because there is only one and common substrate in the circuit), we always must connect it to the lowest supply to make the diode Psub-Nwell in reverse.
Why do we want to reverse the Nwell-Psub junction...
Hi Dominik,
I simulated the solution with pchannel-nwell junction (please see attached pmoschannel_simu_diode_results and pmoschannel_sim_testbench), I explain the results as follows, the source and the drain ohmic contact behave like two diodes with the Nwell, and the sum of the two currents of...
Hi,
How to design a bridge of 4 diodes in cmos process (nwell psub)?
I simulate the structures of bridge rectifier ( that i find in papers) but it doesn't work.
Thanks,
Hi dick_freebird, It looks a good solution for my soft limiter. I googled source-follower cross-clamp but I don't find more information about it. Can you please give some references (papers or books...) about it? Thanks a lot,
Hi Dominick, I want to use it for a soft-clipping amplifier with two back to back diodes in the negative feedback path of an amplifier in parallel with a resistance, the function of the circuit is limiter/compressor to have the loop gain superior then equals to unity in absolute magnitude.
I...
I said that the pmosfet solution doesn't work in CMOS Nwell Psub process because :
- the desired junction is p+(drain)- Nwell, knowing that diodes are in the feedback of the AO-amp, in the case of diode "1" with Vp connected to Vout and Vn connected to virtual ground (INN of AOPAMP), the...
Hi all,
The question is about the soft clipping stage of an oscillator integrated circuit designed with Cadence Virtuoso. The technology used is CMOS and the process is AMS 0.35um.
I want to design a back to back silicon diodes in the negative feeback path of an op-amp in CMOS technology. The...
Hi all,
To specify more my problem :
For every resistor model of the AMS C35 process design kit , for instance "rpoly2" : there are the "rpoly2" model and a "rpoly2c" model.
"Rpoly2c" (in schematic view) is with 3 terminals (plus,minus and Ref) and it is made by 2 "rpoly2" instances (in...
Dear all,
I use in my schematic and layout (Cadence Virtuoso IC6) 2 same components (rpoly2,Lib PRIMLIB, tech AMS0.35). And, when I create the av-extracted view with QRC ASSURA, this specific component model become another model ( rpoly2c, it is the same model with parasitics capacitances to...
Hi everyone,
I am using TSMC18 with Cadence IC6, and when I run Assura LVS, Schematic and Layout match, But when I run Calibre LVS, it finishes with "Nothing in layout".
To know the origin of this problem : I flatten my PCell, and when I show the properties of some layers (with Q) I have in...
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