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Recent content by t4_v

  1. T

    Bandgap voltage variation in different corner

    I would look into the schematic and see voltages and currents to compare FF vs TT to find the reason. The bias current that biases badgap (opamp that is used in the bandgap) varies with corners and it affects the final bandgap voltage.
  2. T

    Comparaor offset measurement

    If I remember correctly the .dc sweep must be done from min to max value (voltage range on X-axis) with a given step and then back. .The op point calculated for a given step should be used to calculate .op for the next step.
  3. T

    Matching considerations

    In my opinion, they are equal. Make distortion on Y-axis and X-axis and see that both matchings compensate the distortion in the same way. For example distortion on X-axis (rises in the right direction by 1): 1 2 3 4 1 2 3 4 and the distortion on Y-axis (rises down by 1): 0 0 0 0 1 1 1 1...
  4. T

    Amplifier 2nd second stage topology clarification

    Where exactly would you like to put the 2nd amplifier?
  5. T

    Stuck at simulations of Amplifier in LTSpice

    What you have is Vin = Vg = 100uV What is the voltage value on resistor R1?
  6. T

    Rail to rail circuit simulation

    For opamp design, yes but you need PGA so an opamp with programmable gain as: - Vin = +/-1 V -> Vout = +/- 3.3 V -> gain = 3.3V/V - Vin = +/-3.3 V -> Vout = +/- 3.3 V -> gain = 1V/V For comparator your picture is true, except the fact that output should be a rectangle signal...
  7. T

    What are the typical lab characterization equipment used for testing Analog ICs?

    Chips from MPW wafer may be tested on a probe station (wafer or alone chips without closed casing).
  8. T

    Rail to rail circuit simulation

    If you want to design CMOS IC opamp (because it is not clear to me what are you want to do) an example list of simulations may be as follows: Source: https://payhip.com/b/5Srt ("Preview" button in the top right) It is rather full list of possible simulations. It depends on the design, to...
  9. T

    sizing of floating current sources in folded cascode amplifier ?

    It is a hard question due to the complexity of your architecture. Start with L = Lmin or L = 2 x Lmin so for high voltage domain 3.3V that would be 0.35 um or 0.7 um, respectively. Why you are using such architecture? Cannot you start with the simpler variation of your architecture and then...
  10. T

    sizing of floating current sources in folded cascode amplifier ?

    You would rather want to size them in a following manner: P7 = P8 N5 = N6 By selecting W/L of N6 and P8, you set the gate voltages of output transistors N9 and P11. Hence you are rather looking for such situation, where: - ID_N6 = ID_P8 = 1/2 ID_P6 - output quiescence currents ID_N9 = ID_P11...
  11. T

    Trends in Analog IP for ASIC Design

    All IPs are used. Otherwise, companies would not sell them. Try looking for companies that offer IPs to see what is the market. USB, MIPI, HDMI ... so on, so on.
  12. T

    Layout of big transistors

    It's like with your current mirror in another topic. Just depends and different persons use different numbers. Just go with 10, then try 20 and see whether everything is ok. In case of layout if you break W = 100 um into 10 x 10 um, everything should be ok. However, if you break W = 100 um into...
  13. T

    Implementation of Operational Transconductance Amplifier in LTSpice

    Show us your "straight line", that is, the simulation results.
  14. T

    Implementation of Operational Transconductance Amplifier in LTSpice

    Hard to say for me, as the last time I used BJT except bandgap was years ago during studies. I would need some time to verify your calculations. Just try to run simulation and verify them. If there is anything else I could help you, please write. :)
  15. T

    Leakage currents in nano meter scale CMOS processes

    True. Good advice. Anyway, books or any resource is good just to give an rough idea.

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