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Re: Regarding LATCHUP
there are 2 bjt in a latch up model. PNP and NPN. in the model, the substrates/well are connected to the bases of the BJTs. if there is enough voltage drop in the wells, there is a possibility that these BJTs are triggered because these wells are directly connected to...
Re: differntial pair
yeah u might be right... but this diff amp is used in high speed applications... this capacitance ( i think ) is not beneficial since it has an effect to the speed of the system. correct me if im wrong again... ur comments will also be anticipated and appreciated.. thanks...
Re: differntial pair
thanks.. you are right.. but when the 2 diff lines are close to each other, parasitic capacitance would be seen bet the lines.. do u know any technique to avoid this parasitic except to put a dummy path/line between them? if a had to use different metals in routing the...
Re: Capacitor
in DC, when the capacitor reaches its peak voltage, charging stops thereby stopping the flow of DC . whereas in AC, when the capacitor reaches its peak voltage, AC changes its polarity and discharges the capacitor. this repeats as fast as the frequency of the source. this cycle...
Re: differntial pair
if big spacing between diff lines are drawn, noise that might be injected to one line is different from the other one. how could this be avoided?
Re: differntial pair
yeah u are right.. but how about the differential nodes? how can i reduce the parasitic capacitance between them? putting extra lines between them may do, what else?
Hello!
what are the techniques to consider in laying out differential pair/differential nodes in a high speed application?
any idea?
thanks and regards,
sxunxs
Re: Dummy connection
yeah, dummy should not be connected to the functional devices because it disturbs the ac signals flowing through it.
PMOS should be connected to VDD and NMOS to VSS; i mean all of its terminals.
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