Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I have scan mode both scan shift and scan capture STA pass, and Zero delay gatelevel simulation pass, but the simulation annotated with SDF fails, I use the same SDF check timing ,there is not timing violation, why the scan shift fail? I think STA clean means scan shift should be OK?
the problem is these memory only occupy limited space of the memory space,so when not access, all 3 DOUT will be Tri-state, which is not good because it use internally, Tri-state can cause learkage issue. if I have a decoder always enable one BANK, since the all OEN enable almost switch...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
