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hi guys,
I'm just studying the verilog, and got something very wired in case statement. The followings are the code, and it's very simple:
always @(*)
begin
casex({aluop_ex, funct})
6'b000??? : alu_ctrl <= 0000;
6'b010000 : alu_ctrl <= 0000;
6'b010001 : alu_ctrl <= 0001...
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