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Recent content by SVTONY

  1. S

    debussy install in Fedora1.0

    At least I know it works on Fedora 1.0. Not sure about 2.0
  2. S

    Combinational or Sequential? A question about "Process&

    Re: Combinational or Sequential? A question about "Proc Because the first one has the clock information and the second one does not.
  3. S

    SIMULATION MODEL for 32M Flash

    samsung nand flash model I think the contents of the NAND flash model is protected using Cadence's approach. And the modelsim could not read that in. You need to use Cadence's Verilog-XL or NC-Verilog to run the simulation.
  4. S

    Doing LEC for Altera Stratix device

    Can any one tell me whether it's possible to do LEC (formal verification) between RTL and the synthsized netlist, where the netlist is generated by Synplify for Altera Stratix deviec? I tried to find the appropriate library to load in order to do the comparison. However I still can't find...
  5. S

    How to change Synopsys installation directory??

    I believe Synopsys uses absolute path for file link. That's why the program won't work after you move the tool around. Maybe you could just re-install the tool.
  6. S

    Microcontroller Trainer Design

    I think you need to consider whether you want to discuss just one micro-controller or various types. Different micro-controllers have their own special characteristics. Usually you can find a lot of examples from manufacturers' application notes.
  7. S

    debussy install in Fedora1.0

    If you choose to install everything, the library file will be there.
  8. S

    Error while loading shared libraries in CDSDOC on Linux

    Re: cdsdoc on linux? I had no problem using Linux 9 or Fedora Core 1 to run Cadence tools. Check your settings.
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    REDHAT 9.0 work with EDA tools

    Is there any one who can run C*A*D*E*N*C*E B*U*I*L*D*G*A*T*E under RH9? Every time I started the b*g*_*s*h*e*l*l program, the program crashed with "===>ERROR: An unrecoverable exception has occured (SEGV)."
  10. S

    Dump ".fsdb" in modelsim NT version?

    dump fsdb in modelsim If you don't need to use additional PLI, you are supposed to be able to use the included novas.dll to dump fsdb file. Look for the document in your installation.
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    How to deal with high-fanout nets using DC

    high-fanout net + synthesis Actually it will depend how many cells the reset signal is gonig to. If you want to let the synospys DC to add buffers for reset signal, use set_max_fanout 20 your_design, something like that. And use balance_buffer command to insert reset buffer after synthesis...
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    Already have FPGA compiler, why need Design Compiler (DC)?

    Design Compiler Can design compiler do FPGA synthesis? I mean if there are the library cells for those FPGA devices, could we use DC instead of FPGA compiler. I am more familar with traditional scripts than the graphics GUI.
  13. S

    Looking for FPGA tools that does DFT

    FPGA with DFT Sorry fo the confusion. What I want is Windows-based FPGA tools that can not only translate RTL to FPGA cells but also insert the scan-chain (or JTAG). We would like to verify that the JTAG (or the scan chain) is inserted correctly and the system can work with external...
  14. S

    how to manage multi license in linux!

    linux multiple license servers lm_license_file You can do in either way: 1. start each license individually lmgrd -c license1.dat lmgrd -c license2.dat .... 2. merge the license files together into one big file lmgrd -c biglicense.dat Make sure the SERVER line and DAEMON line...
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    Help me solve current leakage in a design

    Thanks for the suggestions Thanks you all for the suggestions.

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