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Recent content by sutapanaki

  1. S

    GBW and -3 dB relationship

    I don't think so. If you are talking about the folded cascode you showed previously, it is still the ac current of the input diff pair that charges the compensation capacitors, so it is still gm/Cc. And I assume the non-dominant pole will be at the output of the class AB stage, plus other...
  2. S

    GBW and -3 dB relationship

    The GBW depends on the gm of the 1st stage and the Cc. It doesn't depend on the DC gain because you have the gain and BW trade-off. If you increase DC gain, your dominant pole gets lower and vice versa - if you decrease your DC gain your dominant pole gets higher. The product of the two stays...
  3. S

    GBW and -3 dB relationship

    I don't understand what you mean by booting it up.
  4. S

    GBW and -3 dB relationship

    Yes, if you use simple 2 stage ota the gain, or rather the loop gain will drop when driving resistive loads, but that dosn't mean the GBW of the loop will drop. The DC gain will drop but the dominant pole will increase, so very likely the GBW will stay roughly the same. Remember, GBW=gm1/Cc and...
  5. S

    GBW and -3 dB relationship

    I think this topology is not fit for a high frequency operation. First you have your cascode nodes which contribute non-dominant poles. Then you have the translinear loops to bias the output stage which are also not super fast. Usually people use just a simple 2 stage Miller OTA for high...
  6. S

    GBW and -3 dB relationship

    That's a lot of increase. You will need 2x gm, which 4x the current. But increasing the UGBW by that much you will probably aproach the non-dominant poles and run into stability issues again. I am afraid your goal doesn't require just a simple tweak.
  7. S

    GBW and -3 dB relationship

    But before you reached the limit of stability you were reducing Cc and then did you get higher UGBW?
  8. S

    GBW and -3 dB relationship

    I assume the plots on #10 are for the loop gain. Are you saying that if you decrease the Cc without changing the bias current you don't get higher frequency where the frequency response crosses 0dB?
  9. S

    GBW and -3 dB relationship

    Maybe you can plot or draw something to show what you are doing and what you are getting.
  10. S

    Sampling switch uses a bootstrapping technique

    Yes, exactly. Bulk of M3 has to be connected to CAP_P. And correctly stated that M7 won't turn on when having high input voltages because its gate is at VDD.
  11. S

    Sampling switch uses a bootstrapping technique

    So, you are confirming what I said in my first comment in #2 that right after sn goes high it is the M7 that pulls down the gate of M2, after which M10 takes over. Now, if you remove M7, what will pull the gate of M2 down initially?
  12. S

    Sampling switch uses a bootstrapping technique

    since you have all the simulations, can you tell me what pulls the gate of M2 low and the gate of M10 high right after your clock goes high?
  13. S

    Sampling switch uses a bootstrapping technique

    It is a bootstrapped switch and is used for input voltage from 0 to Vdd.
  14. S

    Sampling switch uses a bootstrapping technique

    I wouldn't remove it. M7 source is connected to the input signal while the gate is at fixed Vdd. So, the Ron of M7 will vary with the signal and will modulate the Ron of M2. M10 has more or less fixed Vgs, In order ot have the bootstrapping action you need to pull the gate of M2 down to turn it...
  15. S

    GBW and -3 dB relationship

    Junus2012, you should be clear what you are talking about and how you look at things. Since you have a feedback amplifier, then you will have to deal with the loop gain. UGBW is something related to the loop gain and the DC value of the loop gain will also define the accuracy of your closed loop...

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