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Recent content by sushl

  1. S

    PLL implementation through FPGA

    Let me rephrase my requirement sorry.. ignore the earlier code. I am trying to implement a phase correction verilog module for two clock inputs coming into my cycloneiv fpga. My module has Two clock signals, clock_1 and clock_2 with frequency 8Khz from different clock sources that are input to...
  2. S

    PLL implementation through FPGA

    Hi FvM 1. Intended phase resolution. If it's better than 1/25 MHz, you need a higher clock frequency or analog phase interpolation means. I'm okay for the phase resolution to be 2-3 clock cycles. about 120ns. 2. Fast locking versus noise immunity. Do you plan different filtering for...
  3. S

    PLL implementation through FPGA

    Yes which is why i need to modify the logic to start and phase align the standalone clock signal_2 with the signal_1 and pass it out through pll. Been looking up loop filter, vco counter approach and tried to implement it through code. here is my implementation. module...
  4. S

    PLL implementation through FPGA

    Hello All i'm looking to implement a PLL with the following specification through rtl code. Requirement: Develop an RTL PLL (phase-locked loop) logic with holdover functionality to ensure continuous phase synchronization of the output signal (pll_out) to the reference signal (signal_1) even...
  5. S

    PROCESSOR IS REBOOTING when hotplugging usb console to processor's Board through UART

    Hi Klaus, We successfully resolved the issue, we placed a 0.01uf cap on tx and rx lines;
  6. S

    PROCESSOR IS REBOOTING when hotplugging usb console to processor's Board through UART

    Hi Klaus, We don't have any onboard FTDI chip, we are using a external USB to UART converter(FTDI-232). We tried connecting and disconnecting, with GND line connected always, Still the board is Rebooting. We are using Processor IPQ4029 has anyone faced any issue on this chip?
  7. S

    PROCESSOR IS REBOOTING when hotplugging usb console to processor's Board through UART

    Hi All, while hotplugging(5-8 times) FTDI chip usb-uart console onto my laptop; the processor reboots, this rebooting process is intermittent. the processors uart lines are connected to the consoles uart lines(I/O level 3v3 both processor and console); currently on the uart's TX and RX lines...
  8. S

    ADC internal Reference voltage

    Hi all, we are using ADS1015 ADC its 12 bit adc (Vadc/Vref)*4095= adc digital value. for analog inputs we can give a voltage anywhere between ±0.256 ±6.144 V. not able to do find the value of Vref. how to find the typical value of Vref so we can substitute in the above formula and correlate...
  9. S

    Output of exors are showing x in EDA playground

    Thanks FVM. I have mistakenly considered the input's inA and inB as wire's ; i have rectified them it works now. :)
  10. S

    Output of exors are showing x in EDA playground

    Hi all , I've tried a simple EXOR verilog code along with test bench on the EDA playground, test bench is forced with inputs 00,01,10,11 respectively ; can anybody tell me why were not getting correct outputs? all are showing x,x,x,x in the LOG. Here's the link to page...
  11. S

    To swap bytes 0 and 1, and 2 and 3 of a 32-bit word, use the idiom as

    Hi , can anyone explain me the logic of this IDIOM (((x&0xff)<<8)¦((x&0xff00)>>8)¦((x&0xff000000)>>8)¦((x&0x00ff0000)<<8));
  12. S

    FPGA and processors working

    Thanks Are there any designs where i can find and understand the usage of both FPGA and Processor together, on a peripheral level.
  13. S

    FPGA and processors working

    Hi All, I was hoping to get some insight as to why FPGA's and Microprocessors are both used together on the same board. I would like to start from referring to some already existing FPGA-Processor designs(Eg Artix with an SOC ) , can anyone point me towards that direction by providing links? It...
  14. S

    How does feedback loop control the duty cycle of buck regulator

    Hi all Thanks for the replies; please find the attachment, the regulator is operated in current mode, it consists of an internal clock generator, error amplifier and current sense. I have 2 questions The error signal is compared with the current slope ramp signal and that is given to the...
  15. S

    How does feedback loop control the duty cycle of buck regulator

    Hi All, While going through internal structure of a buck regulator, there was a feedback loop connected from the voltage divider circuit therein connected to a comparator and the input fed to the SR flipflop R end. How does this feedback control the duty cycle ?
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