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Recent content by surendraeda

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    What issues can be faced while each Physical design stage

    Re: What issues can be faced while each Physical design stag See link https://digital-ic-design.blogspot.com/2007/11/physical-design-flow.html
  2. S

    What issues can be faced while each Physical design stage

    while+each It is very broad question,May you can start looking at PD materials first.For sure you will get clear picture once you work on atleast 2 to 3 designs.
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    Chip Ring & Core Ring

    core ring Core ring is the ring over the boundary of floorplan which is is used for uniform power supply to the full die area.
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    Question about crosstalk optimization in Celtic

    Re: Celtic- optimization Hi, delay due to crosstalk effect can be reduced by upsizing the cell or applying non default rules likw(double spacing) on net metal routes or shilding. So you can check what it is doing by inspecting both before and after optimizations.
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    X-talk is dependent on frequency?

    Hi, Only cross talk delay afftects frequency. Crosstalk noise may cause functional failure.
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    How to calculate die size for given macros and memories?

    die size calculations Can any body explain some examples on how to calculate die size for given details of macros and memories.
  7. S

    STA-max-freq Calculation

    max frequency sta Why is Hold time neglected while calculating Max Frequency?

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