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Recent content by suquid29

  1. S

    == vs >= : area wise

    Hi I was wondering what is the different, area wise, between >= and ==. Lets say I want to start switch state in FSM (verilog, asic) with the condition cntr_t >= 4'h8. (the counting is with a bit faster clock, so in the edge I'm checking it, it sometimes will be 8 and sometimes 9; there is...
  2. S

    JTAG - try JTAG on RTL

    Hi, I have a design that has a ARM11 core. Is there an easy way (free?) to connect to the JTAG pins, and run some commands (IDCODE etc.)? I didn't find anything online.... yet.... Thanks!
  3. S

    vpd dump files in VCS

    this is correct. but i want to know what time interval was "recorded" by each vpd, w/o open it. lets say i have a problem in the simulation log in 1977885ps, but i have 5 vpds. i want to be able to know which one i should open....
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    vpd dump files in VCS

    Hello, When I'm running a long simulation, I get a few vpd files of 2Gb. Is there any way to know what time interval each file has "recorded"? e.g. file_01.vpd 9000ns- 12500ns, file_02.vpd 12500ns- 22500ns etc. Thank you!
  5. S

    What to do "between jobs" ?

    Hello, I'm an FPGA engineer (1 year experience), lookin for a new position now. That can take a few months. What do you recommend doing in all my spare time? (as for technical knowledge/experience) learning script language / read thoroughly xilinx manuals / learn more tools etc. Thanks...
  6. S

    Clock and data on VirtexII pro

    Thanks for the full answer. Does the fact that clocks using special resources (faster lines) than the data should affect? If not, I'll just continue with my RTL and try to synthesize after. Hoping not to get wired warnings :)
  7. S

    Clock and data on VirtexII pro

    Hi, I'm implementing a circuit on VirtexII Pro where I need to connect clock signal to the D input of flip flop. (both data and clock are clocks, but not the same). Is it possible? Will the synthesis tool (XST) accept it? Thanks!
  8. S

    Question about comparator timing

    Re: Comparator timing thanks! is there any way to have a good estimation before starting the flow? (i need only max time) other parts of the design depends on this compare result... thanks!
  9. S

    Question about comparator timing

    Comparator timing Hi, I've used Xilinx corgen 10.1 to generate instantiation for a 5 bit comparator (simple, output not registered) for VirtexII pro. How much time will pass from the inputs change till the result is valid? I cant get it from the datasheet. I dont need exact time but the top...
  10. S

    Xilinx DCM variable shift delay

    hi, i'm looking for a simple VHDL code that can change the DCM phase delay in "real time" (dynamically). couldn't find one on the web. thanks!
  11. S

    XUP Virtex-II Pro board - access with DLP

    Hi, I'm using (at the university) an XUP VirtexII Pro board with DLP interface (https://www.dlpdesign.com/usb/usb245.shtml) . I looked everywhere but I didnt find how to code the register in VHDL that i could configure through the DLP. I'm looking for a working example of register code (and...
  12. S

    How to know if clock is toggling?

    I'm not sure I've fully understood what you mean.... Can you please explain again? Thanks ! And one more question: I'm using a clock i don't know if exist as a clock for a process. If it suddenly stops, I can get the wrong status. right?
  13. S

    How to know if clock is toggling?

    Hi, I'm designing a module that measures frequency of unknown clock. I've done it simply by counting edges on a known period of time window (with proper synchronization of course). But before that, I need to check if its toggling... How can I do that? I though of OR between clk and NOT(clk)...
  14. S

    Synchronizers on FPGA (more requirements)

    According to the docs, DCM can delay only clocks. What did you mean by perfect? :)
  15. S

    Synchronizers on FPGA (more requirements)

    Clarification: I need to be able to delay both clock and data with good res. Can this be done by DCM?? VirtexII-Pro docs can be found at: https://www.xilinx.com/support/documentation/virtex-ii_pro.htm
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