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tilling ic design
I'd like to know if you do tiling for your analog blocks to meet the metal density rules. If so, how will the filled metal patterns affect the circuit performance and what shall I pay attention to that?
In my opinion, I prefer to no metal filling over the poly gate and...
Did you ever try the "Edit in Place" feature in Virtuoso? (Layout view menu: Design --> Hiearchy --> Edit in Place). In this way, you can down to the subcell you selected for editting, while figures in all the other cells surrounding are not selectable, but all displayed, so you can easily...
What's the general techniques for crostalk protection in digital layout? Same as that for substrate noise isolation? Or shileding as well? Or anything else?
psub_stamperrorfloat lvs
Did you connected all the psub contacts to vss with metal lines in the layout? Sometimes we put psub contacts in different places, be sure to tie them together.
1. Leakage there is Ioff as indicated by VGS=VBS=0 and VDS=VDDMAX.
2. Our spice model is from GRACE, no leakage model available
3. The circuit is a bandgap with just 0.8uA current. Typical Ioff should be in the order of 1pA~1nA/um. Large leakage at high temperature will destroy the normal...
If a spice model gives out incorrect leakage for VGS=VSB=0 and VDS=VDDMAX,
How to change the spice model to reduce this leakage?
What are the parameters critical to this leakage?
Tryagain, would you pls advice what's the best ways?
We use common GND and power supply pins for analog and digital blocks, but the power lines are seperated from pads to various blocks. As for the decoupling capacitors, shall we connect them between the power supply and ground lines for the...
Does the dummy capacitor on the edges need to be the same size as the unit capacitor? Can we use the dummy capacitor as minimum size according to the design rule, while keep the space between it and the main capacitors same as that between the other main capacitors?
By the way, for double poly...
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