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Hello,
I have just started learning Primetime tool
Can someone tell me about library files that are to be included with the design?
Do we generate those lib files or we download it from company websites,I got mixed messages, somewhere I read that we create these files using lc_shell, and ncx...
thank you, that cleared my doubt in codes 1 and 2.
But can you please explain what exactly happens after we add delay....i mean can you give me a line by line explanation after addition of delay in third code
1)module enum_test;
enum {red,green,blue,yellow} c;
initial
begin
c=c.first;
forever
begin
$display("%s %d",c.name,c);
if(c==c.last)
break;
c=c.next;
end
end
endmodule
2)module enum_test;
enum {red,green,blue,yellow} c;
initial
begin
c<=c.first;
forever
begin
$display("%s...
okkay but what is its significance?
can't we just write that code without using signal?
i mean directly output<= output +'1';
aslo if we take the above code then why the statement output<= count written after end process?
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std_unsigned.all;
entity down_counter is
port (
clock: in std_logic;
reset: in std_logic;
load_enable: in std_logic;
load_data: in std_logic_vector(3 downto 0);
output: out std_logic_vector(3 downto 0)
);
end...
In vhdl code for counter why do we assign signal count value to the output of counter after end process statement
for ex
counter code....
.......
end process;
count<=cout;
thank you
i think i misrepresented my question
see, i have a vhdl code whos output has to be used as input to an another vhdl code
so i want to connect two codes that way. please help me with that
thank you
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