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Recent content by sugubai

  1. S

    base number multiplications

    base number multiplication sir how to give the base number 3, 4, 5, 6, 7, etc., to verilog coding. i try the base number multiplier i have a doubt on how to write on base number? oct number will give on waveform but what about other base value.
  2. S

    Conversion of octal to decimal

    thk u sir for ur advice.. i tried my best.. i convert that octal number into binary and then bcd... next step is multiplication that is (0001 0000 0110)*(0110) in this 0110*0110 the code is module ily( input [11:0] a, input [3:0] b, output [7:0] p ); wire...
  3. S

    Conversion of octal to decimal

    sir please help me sir...if u know how to write the code of verilog for this please provide me
  4. S

    Conversion of octal to decimal

    its octal number multiplication.. tha is (106)base8*(6)base8=(644)8 it is normal octal multiplication we all know... i need the verilog code for this step step which means that that octal number will be converted into binary and then bcd and we multiply the one by one bit that is bcd value are...
  5. S

    Conversion of octal to decimal

    actually i need to convert octal number to binary using verilog..can anyone provide me the code for this conversion. Thanks in advance.
  6. S

    Conversion of octal to decimal

    Re: conversion of octal to decimal Sorry, I confused. it is a binary number.
  7. S

    Conversion of octal to decimal

    need help frds.. want some idea or verilog code for conversion of octal to decimal... the octal number is (106) base 8 and its binary number are (001 000 110) base 2 all we know..but how to write the verilog code for it.. i tried but it has shown some error... the code is module hgf(oct,bin)...
  8. S

    Verilog code for mod 3 4 bit asynchronous counter

    Re: Help me to write verilog code
  9. S

    Verilog code for mod 3 4 bit asynchronous counter

    Re: Help me to write verilog code the mod 3 structure is here..pls help me to write the verilog code
  10. S

    [moved] How to clear Verilog HDL error

    Re: How to clear Verilog HDL error Okk sir.. i am the beginner of the verilog so, now only i am just learned about it..anyway thank you sir
  11. S

    Verilog code for mod 3 4 bit asynchronous counter

    pls anybody help me to write the VERILOG CODE for mod 3 4 bit asynchronous counter using structural modeling..
  12. S

    [moved] How to clear Verilog HDL error

    Re: How to clear Verilog HDL error module kj(j1,l1,j,k,clock,reset,q,qb,q1,qb1,b); input j1,l1,j,k,clock,reset; output reg q1,qb1; output reg [3:0]q,qb,b,a; always@(negedge clock) begin case({reset,j1,l1}) 3'b100 :q1=q1; 3'b101 :q1=0; 3'b110 :q1=1; 3'b111 :q1=~q1; default :q1=0; endcase...
  13. S

    [moved] How to clear Verilog HDL error

    module kj(j1,l1,j,k,clock,reset,q,qb,q1,qb1,b); input j1,l1,j,k,clock,reset; output reg q1,qb1; output reg [3:0]q,qb,b,a; always@(negedge clock) begin case({reset,j1,l1}) 3'b100 :q1=q1; 3'b101 :q1=0; 3'b110 :q1=1; 3'b111 :q1=~q1; default :q1=0; endcase qb1<=~q1; end always@ * begin if(q1==q1)...
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