Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
So you expect someone else to just write the code for you?
Oh, look some people have written code and posted it on the internet...Did you click on the link in my previous post #4, it gives you a lot of google links to pages that have verilog code for a JK flip flop of varying levels of quality. Some of these examples are downright wrong as they misuse blocking statements in a edge sensitive always block.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.