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Hi Wan,
Do you also combine the Xtal oscillator?
It seems that you simulation PNoise with Xtal Osc,
since the low frequeny noise?
Am I right?
In my experience, it takes several days to get the
loop stabe. you must have a good workstation.
Is there anybody hear about Zero Cycle Slip?
I've checked a lot of paper, but don't find the definition.
The only one is about intergal Zero Cycle Slip, it means the spread sprectrum
average frequency is equal to center frequency for a long time.
Is it the right definition?
Do anybody know how...
Could you tell me how to simulae PNOISE?
Do you run all the circuit or using behavior model?
It seems to take a lot of time to wait PLL to be locked.
Do you take much time to get the result?
Re: Assura RCX Problem
Thanks,
I have looked into p2lvs file.
This file defines the sheet resistance of Metal X.
It doesn't contain any information about blocking.
example
pro_layer=metal1 ext_layer=metal1 sheet_res=(0.0988,0.175)(0.0942,0.3739)(0.0917,0.6939)(0.0907,1.014);
besides, the...
caps2d rcx
Hi,
I have problem in doing Assura RC extraction. When I finished layout
and did the RC extraction, I found there was a large capacitance between
input and output.
I thought that it might be some misunderstanding in setting the environment.
the schematic and layout are shown below...
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