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Recent content by sudheer_vlsi

  1. S

    AC performance of LDO

    break the loop anywhere in the LDO. apply test signal and observe the output.Vo/Vi will give the loop gain and phase. from the u can find PM,UGB.
  2. S

    How to improve LDO's transient response?

    ldo response to load transients improve the PM of ur loop.it will halp in reducing the overshoot and under shoot.
  3. S

    design spec of LDO regulator?

    i think its average curre.t
  4. S

    output capacitor of LDO

    Its better transient response and also noise. This cap also decides the stability and pole zero compenastion.
  5. S

    low quiescent current LDO design?

    Lekage itself will be comparable to ur quiscent current. i donno how one can design with 2uA of Current.
  6. S

    On Chip I/V refernce Circuit

    U cant get current refernce without external resitor. u can generate stable voltage refernce that can be converted to current by using a resistor.
  7. S

    need help for getting job in VLSI(Bangalore)

    vlsi + bangalore + placement hi all, please suggest me institute in getting the job in VLSI Digital domain.. i have completed my B.E from VTU. 2006 passed out, with agreegate 72%. i am only intrested in Digital design... can anyone help me in gettin the job.
  8. S

    Operationa Amplfier and DAC

    there are very books from kluwer publications.
  9. S

    Do we have to use external capacitor at the output of voltage regulator?

    Re: PSRR for regulator hi, for good load regulation performance and for esr compensation we need to use the external capacitor in regulator.
  10. S

    Doubts about current consumption of 10bit DAC

    Hi all, i am designing 10 bit DAC.when we go for complete binary,it takes a total current of 1023I.if we go for thermometer code,then also it takes a total current of 1023I. then how to justify,thermometr coding takes more current than binary coded(apart from extra digital power consumption in...
  11. S

    How much Segmentation in DAC?

    Hi all, I am designing 10 bit 100 MSPS DAC.on what basis i have to do segmentation? Theoritically,we can have some tradeoffs on power consumption,INL,DNL,Glitch and depending on that we will decide.it could be either 6+4 or 7+3.which one to take? are there any calculations for that? plz send...
  12. S

    Which Error amplifeir in DC-DC converter?

    Hi all, i am doing PI compensation for the buck converter,in which a resistor=50k and capacitor=2nF are connected in series with the output of the error amplifier.the converter is operating at 1MHz.how to determine SR and howmuch current to push to drive such a big resistor and capacitor?what...
  13. S

    How to decide the Amplitude of the Ramp in DC-DC converter?

    Re: How to decide the Amplitude of the Ramp in DC-DC convert Hi VVV, If the amplitude of the ramp is more,then the error amplifier output swing must be high to get 0 to100% duty cycle.but it has some supply related problem.if the amplitude is too low,it will relax the swing of error...
  14. S

    line reglation and TC of bandgap

    Hi, Line regulation of the LDO means,percentage change in output voltage due to change in supply voltage. TC of the bandgap is represented in PPM/C,which refers that,per degree change in temperature,how many parts in million ur output voltage will change. hope it helps.
  15. S

    What is an error amplifier and how to design it?

    Re: what is error amplifier Hi, If u r designing the error amplifier for LDO,see to it that it has low output impedence.high output impedence may result in dominant pole and may create problem in stabilization.hence its better to keep buffer at the output of the error amplifeir so that it...
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