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Re: False paths
False path occurs when there is no propagation of data along that path.
if u have a path which is very much slower than ur clock, even then there may be occurance false path. Paths from master reset signals are often false for a similar reason. Often reset sequences occur over...
Re: negative timing checks
by saying negative timing checks i mean negative setup and hold times of signals, these timing details are available in sdf file. when the simulator(modelsim) tries to back annotate, whts happening to these timings.
for example... if i take a dff from standard tsmc18...
Re: FPGA design
hi,
if u r getting into fpga design, FPGA advantage suite is really usefull. It helps u in understanding the design better as it includes even graphical view. It has templetes for ease in riting hdl code for the first time. it has simulator which is having very good debugging...
negative timing checks
During timing simulation many a times we do face issues with negative timings checks. when we have negative timing checks, how does the simulator (modelsim) overcome those. Am well aware there are options to make the -ve values set to zero and continue the simulation, but...
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