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Hello
I want to know the difference of all three FVF in the attached diagram. The current source in Fig. a can be replaced by current mirror in Fig. C. This I can understand but what about Fig b. If the current source is is replaced by diode connected MOS. Is the diode connected MOS operated...
Hi
I am using Silterra 130nm for my low frequency analog design. Silterra doesnt provide I/O libraries. Can I use RFESDpads for my design. When I am using RFESDpads its providing good results after postlayout simulation. But Silterra says this I/O pads will not work for VDD and ground. As my...
Hi
I am using cadence software and using silterra 130nm and successfully designed the layout but I am unable to run the post simulation layout. I am using my test bench using symbol of schematic and opened the config view of the test bench. but when I am simulating the post layout simulation it...
Hi
I want to use bondpads in my schematic but I dont have IO pad library. I have rfesdpad library. I am working at low frequency around 1KHz. Can I use this rfesdpad in my design?
Thanx
I have recently start doing layout and came to know that the design rule documents are missing.
I have assuraDRC. tech, assuraLVS.rul file. There are more files with extension .lib etc. Are they not enought for layout design b/c when we run DRC it shows whether the layout is ok or not w.r.t...
thanks for your reply.
I have this techfile.tf in my silterra pdk and it contains the same code. which one shows the x snap spacing and y snap spacing?. Can you help me? is it possible for you to provide this design rules documents?
Hi
I am doing the layout in cadence and when I am running the DRC check it shows an error of "dataAuditErrors". What is this error how can I remove this. I am using silterra 130nm.
Thanks
I cant find the physical design rules. In the PDK documents I have only four files which is related to smart tool kits list of layers and reference manual which is not providing the design rules. Thats what the issue is. From where I can get it now?
Thanks for your reply. Yes I know this. I want to know what should be the X snap spacing and y snap spacing. What values should it be. I am using cadence silterra 130nm.
Can someone help me iin identifying where I can check the x snap spacing and y snap spacing of silterra 130nm? I cant fnd in any document. Does anyone know the X snap and ysnap spacing of silterra 130nm for layout?
I am using SPECTRE. Can you please tell me what is the extensioon file of montecarlo file? I cant find in my PDK? I am using 5.1.41 cadence and silterra 130nm
hello
I am using cadence 5.1.41 and silterra 130nm. I want to run monte carlo simulation. I have to add the monte carlo file for simulation run but I dont know what file I have to add to do montecarlo simulation. Can some one guide me. In montecarlo simulation do I have to always sweep any...
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