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I am simulating a fully differential OTA for a class project. I have the basic specs where I would like them (like gain,BW,PM). But, when I run my transient sims, I am seeing Vout and Voutb are not symmetric. Both are pulled up to about the common mode votlage of 1.1V and then are clipped...
I have designed and had built a 4.9MHz pierce oscillator on an IC. I have it in the lab and everything looked okay for a while. The oscillator seems to start up and have decent frequency accuracy. I have noticed when I put my finger on the crystal pins, the oscillator dies until I remove my...
1. The asymptote should be 9V. I think the graph is off by a factor of 10.
2. I don't know. By the definition of tangent line, you could draw it anywhere on the graph. Perhaps it can be argued that the origin is the most interesting because it will give an indication of the maximum current...
I took another look at the circuit. A couple things I would try.
1. Delay the turning off of your output stage of the opa until after the opening of S2. A couple inv. delays should be fine.
2. Add a charge injection cancellation switch to compensate for charge transfer from S2. See the...
Are you leaving Vp at the proper bias votage? 30mV seems a little high to me.
What is your load capacitance? The bigger your load cap, the less change you should see. Unless I am missing something.
The on/off switch device should be as small as you can make it to reduce coupling cap to your...
As dick_freebird said the problem is charge injection.
For a circuit like this, I would use a pmos switch in series with your current mirror instead of pulling down on the gate of your mirror. If you put it on the supply side, it will reduce the coupling capacitance to VO. Also, make this...
Re: PLL and Jitter
It is possible for PLL jitter to cause timing issues. You may be correct in your statement that it doesn't in your case, but I think you should do enough analysis to back up that statement.
Assuming your capacitor has to charge from 0 to 1.17 twice for a total period. Or charge/discharge to these voltages.
i = C dv/dt
dt = C dv/i
dt = 5e-12 * 1.17 / 10e-6
dt = .585 us
Now to do this twice will be 2 * dt
2 dt = 1.170 us
=> f ~ 855.7kHz
Is the voltage ripple measured with the cap in the circuit?
If not, the ripple should go way down with a large cap out there.
Does your Z account for the ESR?
If not, the series resistance should be added to your z to get your actual current.
One thing you are definitely missing is the fact...
In my mind there are times to use Vdd and times to use Vss.
Anyways, I would like to comment on the idea of using a floating wire as a shield mentioned by baenisch. This would be counter productive.
Floating metal between two traces increases the capacitance between two traces. See the...
The dlmread command will not read in text (must be a numerical value). I am guessing that is the problem. The solution will depend on the file. I will need more information about what is actually causing your problem. create a small file with just a line that is giving you trouble and we can...
use dlmread:
https://www.mathworks.com/access/helpdesk/help/techdoc/ref/dlmread.html
rng = [7 2 10 4]; % get lines 7-10 (fields 2-4) and store in a matrix
dlmtr = ' '; % use this is space is your delimiter
M = dlmread('filename.txt', dlmtr, rng);
% now your data is stored in matrix M
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