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Recent content by sruthi2n

  1. S

    to check 1 in the msb position

    module xchg(n1,n); output [23:0] n1; input [23:0] n; reg [23:0] n2,n9; integer i; initial i=23; initial n2=n; always @(*) begin:cnt for(i=23;i>-1;i=i-1) begin if(n[i]==1) begin i=-2; end else begin n9={n2[22:0],1'b0}; n2=n9; end end end assign n1=n2; endmodule
  2. S

    [SOLVED] addition of ieee 754 format in verilog

    module fadd1(out,in1,in2,clock); output [31:0] out; input [31:0] in1,in2; wire bout; wire [7:0] e1,e2,e,exp; reg [7:0] r,z; reg [23:0] res; wire [23:0] new,n1,n2; reg res1,res2; input clock; assign e1=in1[30:23]; assign e2=in2[30:23]; sub8 cl(e,bout,e1,e2); ssl...
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