[SOLVED] addition of ieee 754 format in verilog

[sruthi2n]

module fadd1(out,in1,in2,clock);
output [31:0] out;
input [31:0] in1,in2;
wire bout;
wire [7:0] e1,e2,e,exp;
reg [7:0] r,z;
reg [23:0] res;
wire [23:0] new,n1,n2;
reg res1,res2;
input clock;
assign e1=in1[30:23];
assign e2=in2[30:23];
sub8 cl(e,bout,e1,e2);
ssl n23(n1,n2,exp,bout,e,e1,e2,in1[22:0],in2[22:0]);
kkl k(new,n1,n2,in1[31],in2[31]);
assign out={in1[31],exp,new[22:0]};
endmodule

module ssl(l1,l2,ex,bo,k,k1,k2,n1,n2);
output [23:0] l1,l2;
reg [23:0] l1,l2;
output [7:0] ex;
reg [7:0] ex;
input [22:0] n1,n2;
input bo;
input [7:0] k,k1,k2;
reg [7:0] r;
reg [23:0] n;
reg [23:0] p;
wire clock;
always @( posedge clock)
begin
if((bo==0)&&(k==8'b00000000))
begin
assign l1={1'b0,n1[22:0]};
assign l2={1'b0,n2[22:0]};
assign ex=k1;
end
else if((bo==0)&&(k!=8'b00000000))
begin
assign r=k;
assign p={1'b1,n2[22:0]};
shift(n,p,r);
assign l1={1'b1,n1[22:0]};
assign l2=n;
assign ex=k1;
end
else
begin
assign ex=k2;
assign r=~k;
assign p={1'b1,n1[22:0]};
shift(n,p,r);
assign l1=n;
assign l2={1'b1,n2[22:0]};
end
end

task shift;
output [23:0] n;
input [23:0] p;
input [7:0] r;
assign n=p>>r;
endtask
endmodule

module sub8(diff,d8,a,b);
output [7:0] diff;
output d8;
input [7:0] a,b;
wire bin;
assign bin=0;
wire [7:1] d;
sub s47(diff[0],d[1],a[0],b[0],bin);
sub s412(diff[1],d[2],a[1],b[1],d[1]);
sub s45(diff[2],d[3],a[2],b[2],d[2]);
sub s46(diff[3],d[4],a[3],b[3],d[3]);
sub s41(diff[4],d[5],a[4],b[4],d[4]);
sub s48(diff[5],d[6],a[5],b[5],d[5]);
sub s49(diff[6],d[7],a[6],b[6],d[6]);
sub s40(diff[7],d8,a[7],b[7],d[7]);
endmodule

module kkl(new,n1,n2,in1,in2);
output [23:0] new;
reg [23:0] new;
input [23:0] n1,n2;
input in1,in2;
reg [23:0] res1,res2,o1,o2;
wire clock;
always @(posedge clock)
begin
if((in1==1&&in2==1)||(in1==0&&in2==0))
begin
add(res1,n1,n2);
new=res1;
end
else
begin
assign o1=n1;
assign o2=n2;
nsub(res2,o1,02);
new=res2;
end
end

task add;
output [23:0] res1;
input [23:0] n1,n2;
assign res1 = n1 + n2;
endtask

task nsub;
output [23:0] res2;
input [23:0] o1,o2;
assign res2 = o1 - o2;
endtask
endmodule

module sub(diff,bor,a,b,bin);
output diff,bor;
input a,b,bin;
wire c1,c2,c3;
xor(c1,a,b);
and (c2,b,bin);
or (c3,b,bin);
xor(diff,c1,bin);
and(c4,~a,c3);
or(bor,c4,c2);
endmodule

can anyone correct the error in this code?I'll add the code for adjusting the mantissa result by left shifting.