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If a C program contains no recursion or reentrancy, the call stack is not actually needed.In other words, stack-allocated variables can be turned into global variables (by the compiler) when there is no possibility that more than one instance of a function may be running at a time. Even though...
Hi All,
Its difficult to find a good collection and one stop for Interview questions in Digital ASIC design. I have started this thread exactly for the same. I would be glad if all of you could post all known Interview Questions, any links or material helpful for interviews.
Let us make...
Hi,
I wrote the following RTL for my I2C project. Dynamic Simulation in Modelsim worked fine for sda_out. But after synthesis I found that sda_out was connected to 1'b1. Also after place and route , the data_in[0] was not connected to any nets.
How do I represent the same in another way...
No. I just read about them in the Advanced ASIC Chip Synthesis book by Himanshu Bhatnagar. I understand the commands of input and output delay and the concept of hold time, but i dont understand how they report the hold time violation when they are set to 0
Hi,
I read about finding hold time violation by giving set_input_delay 0 and set_output_delay 0. How do these help to find the hold time violation of a design?
Hi,
Can anyone explain answers for the following questions?
1. What is the difference between Total Negative Slack and Worst Negative Slack?
2. Does Synopsis DC do the static timing analysis based on the input slope and output cap info of cells present in the critical path of a design. If...
Re: VLSI based project
I guess you can design the following in both VHDL and MATLAB
1. FIR Filter
2. AES or DES Encryption Engine
3. ALU
4. BUS PROTOCOL (Not Sure if you can do this in Matlab)
5. DFT - eg. JTAG
Hi ,
I understand the definitions of set up and hold time. I would like to know what exactly happens in a flip-flop at gate level when set up and hold times are violated? Also any useful and detailed explanation of setup and hold time violation with respect to ASIC design will be appreciated.
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