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Checkout the document iam uploading
go through connecting global nets in soc encounter
Also check out modification of netlist/instantiation
regards
srinivasan
Re: TANNER EDA
Hi
Please dont use tanner. This is one EDA tool which has almost zero support in the Internet. Not many people are using this EDA. If it is not too late pls switch over to someother EDA
I have wasted my precious time and energy with this tool
Friends
I have extracted my GDSII file using cadence soc enocunter 8.1.
I have downloaded and installed a gdsii viewer
Along with the lef and def file,the gdsii viewer successfully imported the gdsii design, but it is not displaying the intended metal layers, via etc properly
rather it is...
Re: short violations
I have not put any routing blockage or placement blockage
Then where is the violation between the wire and cell blockage coming from
Hi friends
iam working on soc encounter
iam designing a digital ASIC
After my place of standard cells and trial routing, i get close to 600 short violations
Can someone tell me how to avoid short violations
Hi
I went through it in detail
I feel there is some problem with the spacing of wire
I have sent the screenshot of the violation browser
Can u check out and help me out
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