Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
How is the output quiescent voltage set ?. As of now, the output leg looks like two different current sources(PMOS and NMOS) trying to force the output node to some value, that is the problem. Your biasing circuit is technically correct but it is not replicating the output leg exactly, the vds...
slow ramp band gap
In general stability analysis can be performed by Middle Brooks Method to find the return ratio and loop gain using a spice simulator. This method involves injecting a small voltage/ current change at a suitable node in the loop and observing the return ratio.
While...
Re: energy in the capacitor
The electric charge in the capacitor is conserved. However to move the electric charge from one capacitor to another work has to be done. The missing 1/4*C*V² is spent for moving the charge from one capacitor to the other capacitor.
Actually i had this doubt in my high school... it is due to the electrostatic loss of energy which is present..... read Griffiths u ll know things better...
Hi all,
I need some help for building A/D converter using Switched Capacitor techniques and the filter is the standard Biquad Filter... try to help me in this regard..
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.