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Hi
i have an hierarchical RTL design placed inside my circuit.
the design has an internal block that i need to force signals upon
is there a way to connect a wire into another wire that is located within an hierarchical block?
Thanks
a digital simulation with digitized analog signals
but i need to keep the interface identical to the analog module so that i could later on replace my model with the actual design
I'm using IES and MMSIM
Hi,
I'm trying to verify a mixed signal design that characterizes a load than applies voltage to that load.
To characterize the load the circuit applies voltage to it than measures it's current.
And in the second phase forces current through it and measures it's voltage.
after taking into...
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