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Hi! Does someone know of any PCB manufacturer capable of doing build-up substrates with <100um vias (and ~6 layers)?
I need to manufacture the following redistribution interposer to interface a flip-chip with 200um-pitch Cu pillar bumps to a standard PCB:
Thanks for any information!
Jorge.
Hi! Does anybody know of any recent paper/book showing the evolution of transistor intrinsic gain (gm*ro) with minimum channel length (=technology node)?
So far I've only found the graph below [1], but I'm looking for other references showing the same trend (i.e. that things get better in 22nm...
Re: Load seen by opamp in non-inverting config. is TWICE w.r.t. inverting config.?
I need an expression of the effective load "seen" by the opamp, to use it as an specification for its design.
You can see my actual circuit in the new attachment below; won't it behave the same as the inverting...
Re: Load seen by opamp in non-inverting config. is TWICE w.r.t. inverting config.?
Yes, I see your point! (a higher resistance means less current, therefore "less loading", right?)
Irrespective of this, my main doubt is if the input impedance counts or not as loading for the opamp.
I...
Re: Load seen by opamp in non-inverting config. is TWICE w.r.t. inverting config.?
Thank you for your reply, Kaus. I am dealing with an inverting switched-capacitance (SC) circuit where the input, feedback and load elements are all capacitors of the same order of magnitude. A reviewer of a...
Load seen by opamp in non-inverting config. is TWICE w.r.t. inverting config.?
Hi! I've come across the result that the load seen by an opamp is radically different depending if it's in inverting or non-inverting configuration. I wonder if I'm making some mistake, or if it's a well known fact...
Hi Dominik, thanks for your reply. I see your point that gds is normally due to CLM, DIBL, etc, but I get the feeling that we are missing something important here: my intuition tells me that, as the inversion level is reduced (by lowering VGS), the channel should become less and less conductive...
Thanks for the reply frankrose. I'm afraid I need something more physical (it's for a journal paper!). Ideally, a general expression that would hold both in strong an weak inversion. So far the best I have found is the following expression from Tsividis' book "Operation and Modelling of the MOS...
Hi! I need a way to show analytically that the output conductance of a MOS decreases as the VGS decreases in WEAK INVERSION. Classical books provide expressions only for STRONG INVERSION, like
gds = IDS/Va = lambda*IDS
Does anybody know is such an expression exists FOR WEAK INVERSION?. I need...
Which models for Huijsing's book "Operational Amplifiers: Theory and Design"?
Hi all! I want to simulate some of the circuits in Huijsing's book "Operational Amplifiers: Theory and Design", but there is no information about which transistor model files to use!
For example, I would like to...
Yes, I'm getting that impression too! I just found the treatment in Baker's book (CMOS Circuit Design, Layout, and Simulation) gives very nice practical details.
If someone can point to seminal/tutorial/relevant papers (class AB output design in CMOS), that'd be great!
Hi! can anyone please recommend references on MOS output stages? In particular class-AB?
I have reviewed the following books, but I'm looking for an alternative view on the subject (= I don't think they do a good job explaining the stuff.)
-Gray, Hurst, Lewis & Meyer (well explained, but...
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