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Recent content by spauls

  1. S

    which is the best tools for place&route?

    ICC is also a better option.
  2. S

    Magma blast fusion & Synopsys DC material.

    Nitin, There are many materials on DC/Magma are posted in forum.
  3. S

    Which one is better System Verilog or E ?

    Re: system verilog/e I used both "Sys verilog" and "e" . well you cant compare simply,both languages are rich in OOPS , while "e" is having advantage of "aspect oriented programming".
  4. S

    FSM for a N/W Processor

    Could you please provide more info on Strobes. I can help you in FSM design.
  5. S

    what is the common synthesis methodology for large scale SOC

    Re: what is the common synthesis methodology for large scale bottom-up is the best for big SoC's
  6. S

    Need book about Synopsys IC Compiler

    Hello, Is there any book avilable on Sysnopsys IC Compiler ? Spauls
  7. S

    timin Violations................plz help

    upsizing wil help to some extent.
  8. S

    Fishtail(Focus) problem

    This is because design does not linked properly. check for "FILE-001" warning.
  9. S

    What are the typical costs of EDA tools?

    Re: Costs of EDA Tools Cost also depends upon no. of licence user and company size. All decided by sales person.
  10. S

    wht are the tools available for DFT?

    Mentor and Synopsys hasa good flow for DFT.
  11. S

    What is chip's reset current?

    could you please clear , what u want. Chip reset current ??
  12. S

    help in encrypting Verilog code

    use AES in Modelsim
  13. S

    semi-custom /full custom

    Semi custom : using 3rd party tools full custom : no third party tools,
  14. S

    How do floorplan and placement affect timing of a design

    if u place timing criticl blocks far , than ur timing got worse.
  15. S

    predictive berkely transistor models

    backannotation sdf syntax back annotation is putting back delays to STA engine and make lfe worst.
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