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Recent content by sorkam

  1. S

    FPGA design ( voltage related)

    can not drive 3.3 V IO pin using 1.8 V source. check that pin minimum input voltagte high level value before connecting any voltage source. i think 3.3 V can drive VIH_min = 0.65*3.3= 2.15V can not drive 3.3V IO pin using 1.8V source. check that pin minimum input voltagte high level value...
  2. S

    AES 128 bit key schedule encryption

    can you add comments in your code
  3. S

    AES algo key generation process in VHDL

    you need to check your code and remove Register Duplication. complete all the loops properly, otherwise it will generate extra component.
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