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Recent content by solsopp

  1. S

    [SOLVED] Biasing and sizing transistors in comparator circuit

    Thanks for your reply. As to why I am implementing this circuit is a long story. The circuit is sort of "home-made". I was originally supposed to implement a ramp ADC from a specific paper. In the paper, there is a clocked reset transistor that resets the cross-coupled NMOS pair (1st stage)...
  2. S

    [SOLVED] Biasing and sizing transistors in comparator circuit

    To mods: since I am unable to edit posts, can you please change the current attachment in the OP to this one? I noticed a small error.
  3. S

    [SOLVED] Biasing and sizing transistors in comparator circuit

    It's comparing continuous time signals. It is supposed to be used in image sensors. Are you asking because you see issues with it? - - - Updated - - - It doesn't seem like I am able to edit posts because I am new. However, I wanted to add additional information. As I said, it's a continuous...
  4. S

    [SOLVED] Biasing and sizing transistors in comparator circuit

    I am new to analog design, and I am currently attempting to implement the comparator given below. It is hard to form specific questions regarding this circuit, as I am unsure of where the problem lies. However, I am sure that my methods of designing the circuit are lacking and maybe incorrect...

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