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[SOLVED] Biasing and sizing transistors in comparator circuit

solsopp

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I am new to analog design, and I am currently attempting to implement the comparator given below.

It is hard to form specific questions regarding this circuit, as I am unsure of where the problem lies. However, I am sure that my methods of designing the circuit are lacking and maybe incorrect. I guess my question is: how do I bias and size the transistors? Where do I start, and how do I go from there? What is the thought process?

I can briefly explain what I've done and how I've thought so far. Feel free to correct me.

1. I started off by deciding (W/L) of the upper current-mirror (M1 & M15). I made sure that the transistors were in saturation, and that the current being mirrored was accurate.

2. I chose (W/L) ratio of the differential pair (M2 & M3) and made sure that they were in saturation.

3. I then chose (W/L) of the cascode transistors (M4 and M5) so that they were in the linear region. I wanted them to be in the linear region to maximise gain.

4. The widths of the cross-coupled pair (M7 & M8) is chosen to be about half of the width of M4 and M5, since nMOS transistors should usually be about a half or a third of the size of pMOS transistor.

So far, I have managed to get the circuit to "function" in terms of switching between high and low states (0 and 1.8 in my case). However, the switching point seems rather arbitrary, since it doesn't switch at the correct value.

Please tell me if more information is needed, or if my descriptions are confusing.
Thanks in advance!

Capture.PNG
 
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sutapanaki

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Why do you use this specific type of circuit? Is this supposed to be a clocked comparator for discrete time systems or is it comparing continuous time signals?
 

solsopp

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It's comparing continuous time signals. It is supposed to be used in image sensors. Are you asking because you see issues with it?

- - - Updated - - -

It doesn't seem like I am able to edit posts because I am new. However, I wanted to add additional information.
As I said, it's a continuous comparator.

IN+ has a constant signal level as input, and IN- gets a ramp signal. This comparator is supposed to be a part of a ramp ADC. VDD is 1.8.
 

solsopp

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To mods: since I am unable to edit posts, can you please change the current attachment in the OP to this one?
I noticed a small error.

Capture2.PNG
 

sutapanaki

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You didn't say why you chose this specific circuit. What I mean by that is you usually use a latch (the cross-coupled inverters at the output) for clocked comparators because there you reset everything, you initialize the input to a sampled voltage (that's why those comparators are used in discrete time systems) and hen you clock, the comparator regenerates and makes a decision.
In the continuous time case you don't really have this happening. Yes, your output will flip, but only after you've built good enough input difference and after the first stage output has changed polarity or is near about changing polarity.. Why don't you start first by simulating only your 1st stage and see how it behaves.
Oh, and by the way you don't get more gain if you have the cascodes in linear mode, if by linear you mean triode.
 

solsopp

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Thanks for your reply. As to why I am implementing this circuit is a long story.
The circuit is sort of "home-made". I was originally supposed to implement a ramp ADC from a specific paper. In the paper, there is a clocked reset transistor that resets the cross-coupled NMOS pair (1st stage). Also,the circuit is actually a regenerative latch circuit that followed another pre-amp circuit (comparator).

We modified the regenerative latch circuit by removing the clock, since clock noise is a big issue for image sensor applications. We also added the NMOS pair at the output stage that is supposed to hold a constant value (transistors M13, M14).

I was told that this modified circuit could potentially work as a comparator, where the signals are compared in the first stage, and sort of latched/held at a constant value in the second stage.

I have done simulations of the first stage only, and it does seem like the switching is very slow, and that the signal levels (from low to high and vice versa) are very small in difference.

So I guess my next question is: since this is a rather unsual circuit... do you see any hope in getting it to work as a comparator?
 

sutapanaki

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If the outputs of the first stage are very low, I suspect that your NMOS cross coupled pair doesn't flip all the way one way or the other and is loading the PMOS transistors on top of it. And if the that's true, then the small 1st stage outputs can't really flip well the 2nd stage latch. People use the kinds of latches you have in the 2nd stage but with well defined 0 and 1 signals that have no problems flipping them. For a continuous time comparator, there is a problem with that. I don't know if you canmake it work, but my feeling is it is going to be unreliable.
 

vivekroy

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Why is the bulk of pMOS connected to the drain? Is that intentional for some reason?
 

nitishn5

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Also,the circuit is actually a regenerative latch circuit that followed another pre-amp circuit (comparator).
This sort of explains the low gain that you are getting.
Fundamentally it looks like you are trying to build a two stage comparator, where the 1st stage is the pre-amplifier and the 2nd stage is the latch.
But your pre-amplifier doesn't have enough gain. The original circuit from which this was taken had another pre-amp corcuit which would have provided the gain.

You can calculate the gain required for you circuit as follows.
If the final latch requires a differential input of say Vlatch_diff to latch
And the minimum differential input you want to resolve is Vin_diff,
The the minimum pre-amplifier gain needed would be Vlatch_diff / Vin_diff

In this condition, since the latch section is also static, it would require a pretty high differential input (Vlatch_diff is high) for it to toggle. Which means that the gain required would be pretty high.

The current 1st stage that you are using has by design a pretty low gain.
As someone mentioned before, cascodes in triode/linear will give a LOW gain and not a high gain.
 

sutapanaki

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I guess, those "cascodes" in linear mode are there to just isolate the kick-back from the outputs of the 1st stage. Even though they are in linear, it still helps. But not with gain.
Yes, the gain of the 1st stage is low because it is loaded by only -1/gm. However, if in parallel to the cross-coupled NMOS transistors in the frst stage there is also a diode connected NMOS transistors, then you have effectively a positive resistance in parallel with a negative resistance and the equivalent resistance increases and so does the gain.
 

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