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i m using 512 point FFT IP core in V6 FPGA to calculate the frequency of the input signal, i m getting the correct peak and amplitude for the same . the peak's real and imaginary value i have to give to the cordic ip core(atan) to get the phase of the input signal . the input to the fft is a...
i am using the multiply and accumulate IP core from Xilinx ,the operation it performs is first multiply the two inputs a and b and give prod= a*b then it subtracts the previous output from Prod
s=s-prod
problem: i m not able to see the s(present) output as it is loop back. in chipscope one of...
hi all,
is there any relation between trace length and phase of a clock signal ? i have to two clock signals of same frequency coming to two devices that should be same in trace length but if there is some difference between the traces then what will be phase difference between the two?
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