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Recent content by snehal.saini

  1. S

    can an input pin of a leaf cell drive an outport of a module directly in DC netlist?

    When I search for all the leaf pins connected to the net of any output port of my module, is there any chance that I see an input pin? I'm expecting only output pins of leaf cells.
  2. S

    Error while opening gvim: Vim E458

    Please help me!! :(
  3. S

    Error while opening gvim: Vim E458

    Hi, Whenever I open any file using gvim, I get the following message: Vim E458: Cannot allocate colormap entry, some colors may be incorrect But.I'm still able to view files without any difficulty. Can anyone please help me how to get rid of this? Thanks.
  4. S

    single foreach_in_collection loop to traverse through two sets of collections

    [Design Compiler] single foreach_in_collection loop for 2 sets of collections I wanted to traverse through two sets of collections with a single foreach_in_collection. i wanted something like: for (i=0;i<10;i++) { A[i] = B[i]; } A & B are the 2 collections i have. Can anyone please help me to...
  5. S

    extracting .sdc from .tcl

    How do I generate .sdc file from .tcl?
  6. S

    removing backslash in a variable in primetime shell

    Hi.. I'm working in primetime shell. I have a variable like: set x top/module/d I want to convert this to top_module_d. tried using "sed" command. But it is giving error when i search for "/". It works well for other characters like "_", "*","!" etc, but not with "/". This is what i tried...
  7. S

    difference between buffer line and buffer wire

    In the timing report, I see Buffer wire (BW) and Buffer line (BL). I was curious to know the difference between them.
  8. S

    IO Timing analysis : how to resolve timing issues?

    yes. it's on IO timing path. So, inserting buffers on clock path also is possible right? I was just curious to know what can be the reason for using inserting buffers in clock path if it's IO path and not using on reg-reg path. Is it because, if buffers are inserted on clock path at the...
  9. S

    IO Timing analysis : how to resolve timing issues?

    I'm getting it after CTS. What I understand is, the only 3 ways to remove violations is : 1. by replacing the driving cell with another cell with more capacity 2. place the cells close by 3. apply buffers in the clock path Please let me know if I am right. and also suggest if there are any...
  10. S

    IO Timing analysis : how to resolve timing issues?

    What to do if a timing violation occurs? Should all the paths be constrained? what to do if i see a path as unconstrained?
  11. S

    negative delay in report_timing

    ok.. thank you... but can the output change before 50% of input pin transition?
  12. S

    negative delay in report_timing

    I see negative delays for few cells in the report_timing report. What does this indicate? this delay has been subtracted in the path delay. is this correct? if yes, why? can anyone please explain?
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