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entity Pulse_outgoing is
Port ( clck : in STD_LOGIC;
reset : in STD_LOGIC;
pulse : out STD_LOGIC);
end Pulse_outgoing;
architecture Behavioral of Pulse_outgoing is
signal count1 : integer range 0 to 100000 := 100000;
signal count2 : integer range 0 to 49000000 :=...
No problems it works but not for what I need my outgoing pulse is well over the 2 ms pulse I need as I want a duty cycle close to 10% not the 70 or 80 this method is giving me. I tried dividing the pulse by 2 but the divide code I tried wouldn't work.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if...
I have tried using state machines and counters with a clock divide but have problems synthesising if I try to use a way for statement or use a rising and falling edge statement in the same process. What is the flag counter?
Hi all,
i need to write VHDl code to produce a square wave output with an amplitude of 2.8v and duration 2 ms every 100 ms as a simulated radar output. Your help will be much appreciated as my lack of Vhdl coding has become apparent.
Smudge
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