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I read the docs related to divider inferred by DC but I couldn't get any specific synthesis settings.
it's really strange.
But I did some other tests which may be useful later for my freinds here. I synthesized the same code with Cadence RTL Compiler and it works properly.
I think But I am not...
I changed it in that way because "/" in VHDL is only defined to signed or unsigned numbers. So I had to do type-casting.
I have disabled all the timing checks. The changes that we can see I think that they are related to the interval result of the divider.
What do you suggests?
Thanks
Yes I am simulating the synthesized netlist.
Something interesting happened, I tried to make the code as simple as possible as below:
library ieee, DWARE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use DWARE.DW_Foundation_comp_arith.all;
use work.lp_package.all;
entity QAP is...
Hello All
Thanks for your helps. this is the code and the simulation results.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity QAP is
port(clk,reset:in std_logic;fL_hlp11:in unsigned(11 downto 0);
fL_hlp111:out unsigned(11 downto 0));
end QAP;
architecture...
If you mean the input is a signed number, fL_hlp11 is an unsigned value.
And I tried for different combinations but it still doesn't work.
Could you please give me more helps?
Thanks.
Hello
I have written a program in VHDL as given below. The pre-synthesis simulation works properly. but the circuit being inferred by DC as “/” is not working properly
and giving the incorrect answers even if the fL_hlp11 is Equal to 0.
ff:process(clk,reset)
begin
if...
Thanks for your help.
Here is my VHDL CODE, I am using N to make the design generic:
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is
generic(N:integer:=4);
port(clk,en:in std_logic;
o:out std_logic_vector(N downto 0));
end;
architecture synth of...
No. no constraints was used during the synthesis. And the output file only includes the instances without any timing info.
- - - Updated - - -
No. no constraints was used during the synthesis. And the output file only includes the instances without any timing info.
Hi
I wrote a very simple counter in VHDL and then simulated to see whether it works or not. Then I sent it to the design compiler to do synthesize without any constraints. after that I made an output netlist in VHDL and brought it back to simulator it didn't work while it was a simple counter...
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