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yes, I have posted this on AMD support. There is a response indicated vivado IP can' t be synthesized by third party tools. The only way is to use a stub file to infer blackbox. I'm trying this new information. The thread in AMD support forum is...
after searching the log, I found a clue: the srr.html file reports
" <font color=#A52A2A>@W: : <!@TM:1707211956> | Malformed decryption envelope in file '........ /dds_sine.v': No known key found in envelope</font> "
it seems synplify can't read this file well. But why? this file is generated...
Hi,
I'm trying vivado with synplify flow. First I tried full vivado flow and this works fine. Then I tried to transfer all data files to synplify. I read all verilog files and xci files in synplify. All seems ok except some IPs failed. These failed IPs are generated by vivado. I just import...
with vivado, I can set this inc file as "global include". In this way every verilog file could know what is defined in inc file. I'm not sure how to do this in synplify
Hi,
I have used `define in several verilog files like
`ifdef FPGA
......
`else // FPGA
....
`endif // FPGA
I use an .inc file to enable/disable these defines macros. In vivado I can set this inc file as "set global include" so that every verilog file see these define macros. Is there is...
thanks for your kind reply. The system can't be changed.
1671793769
The system is like this: In mode 1, the input clock will be ADC in1 for some design with frequency 125MHz while in the other case, the ADC mode changes to 200MHz.
1671793906
I have tried dynamic reconfiguration before. If this...
Hi,
I'm preparing for one design, which connects two MMCM with one clock input port. The input clock port may work at 125MHz or 200MHz, so two MMCMs are used to generate phase-locked 125MHz or 200MHz separately. Is this kind of connection with MMCMs the right design? If so, how should I set...
Hi,
when I run conformal LEC, I met a problem. After "compare" command, I tried to debug my non-eq cells. I tried to run "invert mapped points", but the GUI responds with "Mapping phase cannot be inverted". This confused me. I have tried to set "invert mapped points" in setup mode, before/after...
Hi,
I'm new to conformal lec and confused by some results.
as figure shows a RTL compared to synthesis netlist:
the golden has not-mapped DFF as 21131 while netlist has only 13 DFF not mapped. Does this mean the RTL has so many redundant logic to be optimized by synthesis tool? thanks.
thanks for your comment. I agree with you that trace delay should be checked when setting input/output delay constraints. In fact I also set position constraint so that input/output registers are the nearest one when connecting to the in/out ports. These helps to generate "repeatable" bitfiles...
Of course I have those kinds of constraints in the design. But those constraints can't promise you always get skew balanced bus. That is the reason why I come to ask for help: is there a good way to use constraints to balance bus skew in IO port with FPGA?
Thanks for suggestions with idelay/odelay cells. In fact I have tried that but I don't like that way. The reason is that I need to build up many control registers for those delay settings plus I have measure what kind of delay setting should be. That is a tedious job.
Is there a way to use...
ADC works with two channels, one channel samples at rising edge while other channel at falling edge. Both channel works at 125MHz.
DAC works with two channels, too. Both channel works at DDR way with clock at 250MHz.
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