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Just get a simulator that will do both SystemC and Verilog. I've used both Modelsim and Aldec for this.
The interface is simple...you just instantiate the SystemC piece as a verilog module in your testbench. Your simulator should come with a bunch of examples of how to do this.
Samir
Re: a doubt in verilog
Shouldn't it be:
always@(posedge clk, negedge reset)
The synthesizer probably thinks you're trying to do a logical OR of two edges.
24 V to 5 V DC
It depends on what you are driving with the 5V.
If it is driving a high-impedance input, then you can probably get away with a voltage divider (2 resistors).
If you are driving a low-impedance input, then you'll probably need to do some kind of active circuit to provide the...
SystemC is built into a lot of the simulators now, including Modelsim and Aldec. This means no PLI, and no slowdown in runtime.
The C++ leverage for SystemC shouldn't be underestimated. If you were going to write the same verification suite in SystemC and in SystemVerilog, I believe the...
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