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*series resonant
.options fast
Vin nco gnd SIN (0 1 300 0u)
R nco a 20
C a b 5.897617363u
L b gnd 0.04777070064
.TRAN 1u 1000000u
.print tran v(vin,a) v(a,b) v(b) i(vin) i(r) v(nco,a) v(a,0)
.END
Hi all:
I make a simple RLC series resonant circuit, it shows jXL= -jXC at...
Hi all:
spice simulation tell me
poles ( hertz)
real imag
-1.59158 0.
-79.5759k 0.
zeros ( hertz)
real imag
0. 355.881
0. -355.881
that says there is 2 zero at...
Dear all:
How to measure the rdson during final test accurately ? if the rdson is 5m ohm, the contact resistance between equipments is significant.
Any method to get a certain measure result ?
tks
Dear all:
Could we simulate loop gain and phase by injecting some signal via transformer ?
If possible , could you please show a simple example ?
thanks
Dear all:
I have a liner voltage regulator, I let its phase beyond 180 degree, I guess it should be unstable in transition simulation since it has no phase margin.
But it's not, it is still stable in transiton simulation.
Why the AC simulation can't match the transition simulation ?
Anybody...
Hi all:
how to tell feed back & feed forward circuit ?
I can't distinguish a circuit is back or forward when which vout and vin are connected by other component.
And about miller compensation in a two stage op, the miller capacitor is feed back or feed forward ?
Thanks.
Hi All:
I have a LDO with resistor divider to adjust the output.
I need the LDO output 3.3V for a while than change output to 1.8V.
How to perform that?
I use a switch to change the resistor divider , but the output voltage has a droop before it goes to 1.8v, it is not smooth to the system...
Hi all:
how to simulate in-rush current in LDO design?
In real environment, I use active loading for sink 1A from LDO's output, the turn on the ENABLE pin, the current probe shows there is a inrush current.
But how to perform that in computer?
I tried several ways to model the loading...
Dear all:
I am designing a circuit which can deliver 10A.
But the large current should be difficult to test during CP stage.
Is there any good way to make the current testability?
Thank you.
Dear all:
The LDO has enough phase margin when no load or light or heavy load.
But if I use a pulse current such as
Iout vout 0 pulse( 0 2 800u 1n 1n 100u 200u)
the circuit will ring
And if
Iout vout 0 pulse( 10m 2 800u 1n 1n 100u 200u)
the circuit will be fine.
Why? setting Iout as a zero...
Dear all:
If I have a phase down to -100 deg at 0 db, we say that has 80 deg phase margin.
But, if I have a phase raise up to +100 deg at 0db, how about the phase margin right now?
It is 280 deg phase margin or 80 deg phase margin? or it is a fail circuit ??
Thank you.
Dear all:
I have a clock for duty cycle 30%, if I use DFF divider to get a 1/64 frequency,
the new clock duty cycle becomes 50%.
I need keep the original duty cycle, any method or any FF can help me for this issue?
Thank you very much.
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