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there is no need to make all paths to constrained.
By functional or case analysis statement based, few paths are not active arcs ( means no logic transition is going to happen in that path )
there could be one thing in .lib all the cells by default dont_use, you can remove that attribute in constraints.
try this option in rtl compiler
set_attribute avoid false [get_lib_cell *]
set_attribute preserve false [get_lib_cell *]
MVT libraries contains different set of VT library cells. which will have same feature size, and gate thick ness is varied mainly for leakage power optimization.
synthesis techniques :
generic optimization : logic optimization, boundary optimization, restructuring.
mapped: selecting best...
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