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Recent content by simplybharath

  1. S

    Top block doesn't see ilm's clock tree

    Hi Check using set_propagated_clock before report_timing , this worked for me , seems some problem in the encounter which sets ideal clock
  2. S

    Top block doesn't see ilm's clock tree

    Hi Sir , Did you find the solution for the above problem ? -Bharath
  3. S

    How to reduce a routing congestion in a design?

    Re: Routing Congestion check for cues like utilisation from design_data rpt and cell density maps , i think congestion overall should be fine unless it is concentrated on one spot , if it higher then u have to increase the floorplan area or RTL fix
  4. S

    can increasing overall frequency help in saving GATECOUNT?

    Re: can increasing overall frequency help in saving GATECOU thank you for such a clear explanation :)
  5. S

    can increasing overall frequency help in saving GATECOUNT?

    Re: can increasing overall frequency help in saving GATECOU in your reply u have mentioned frequency ... can you pls explain me in little detail how it can help ? like increasing frequency means reducing the clock period which would require faster gates or more buffers to meet timing ? i...
  6. S

    can increasing overall frequency help in saving GATECOUNT?

    hi all can increasing the frequency improve with reducing the GATECOUNT of the design , iam a newbie , i dont know if it is a proven strategy , can anybody explain me how ? thanks in advance
  7. S

    any good strategy to analyse RP groups and Macro placement

    hi , any good methods/strategies or things to keep in mind for the placement of big cell groups like EBB's and RP's ?? thank you
  8. S

    any method to count flylines

    hi i want no of datapaths going out from EBB's .. iam checking with flylines , is there any way to count the no of flylines going to some particular logic ....iam using IC compiler btw thank you in advance
  9. S

    The command for creating placement bounds of a particular unit in ICC

    what is the command for creating placement bounds of a particular unit in ICC??
  10. S

    saving gatecount in the design

    thanks for ur suggestions, these are fine , can we discuss some strategies wrt placement like if i have many RPD's i can place those cells in such a way that i dont have to use extra buffers to meet my timing , any suggestions on this front will be very helpful for me ... u may think that tool...
  11. S

    What is the half cycle datapath ?

    half cycle path ok , where are this kind of paths used generally ?? whats the logic associated and y ?
  12. S

    What is the half cycle datapath ?

    hi all , can anyone explain what is a half cycle datapath ?? thank you
  13. S

    ILM - interface logic models

    hi , how to use an ILM ?? does ILM help in easing the dataflow analysis ?? pls help
  14. S

    rp group co ordinates

    hi all , whats the command in ICC to get the RP group co ordinates ?? thanks in advance
  15. S

    help in dataflow analysis in ICC

    digital design , actually my problem is , I have moved my macros , i want to analyse their effect on timing and congestion on rest of the units .
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