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For buffers/inverter counts:
*Loosening DRC constraints like transition, cap, max wire length.
*Start with a higher standard cell utilization percentage/smaller floorplan.
*Tweak the delay cells inserted for hold to eliminate overfix, or tweak your hold margin accordingly
Logic Gates:
*Front end logic optimization
these are fine , can we discuss some strategies wrt placement like if i have many RPD's i can place those cells in such a way that i dont have to use extra buffers to meet my timing , any suggestions on this front will be very helpful for me ... u may think that tool does a better placement than manual one but is there a way to find out ??
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