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Thanks for the reply.
However if I wanted to make a core (IP), what I would do is to synthesize using the .db files, import the result to encounter, import the result of the encounter to virtuoso and characterize the design that is imported to virtuoso. How can I be sure that the core is DRC/LVS...
(Reposting this thread as I did not have any replay -- need help on this)
I have downloaded the nangate library and I want to test a layout (that I have synthesized on this library via synopsys and imported it to virtuoso).
How can I run DRC and LVS checks? I cannot find any rule files.
Thanks
Hello,
I have downloaded the nangate library and I want to test a layout (that I have synthesized on this library via synopsys and imported it to virtuoso).
How can I run DRC and LVS checks? I cannot find any rule files.
Thanks
Thanks for all your help.
I will try to use a verilog tb at -f ams option.
For completeness attached is a photo of the schematic (just three inverters connected togeather and I am
trying to use a number of them with verilog view).
Regards,
Thodoros
The netlist does not make reference to the stimulus file stim_testams.tcl.
However I remember that when I had as simulator spectre instead of ams, the netlist file was also not referenced but the simulation was OK.
The stimulus file includes the following:
simulator lang=spectre
_vTin (tin 0)...
How can I post the simulation command file?
What I do to simulate is:
I open ADE and I select the config view of the design.
I set simulator to ams - define connect rules - set stimulus file (via ADE -> setup -> simulation files)
Then I "netlist and run"
---Result shows that the stimulus file...
How can I post the connection of them.
Can you please tell me what files or text is needed?
What I am thinking is that I use connect Rules given by cadence samples (under the insisive package).
However I use umc65nm technology. Is it possible that the rules do not match the technology?
Thanks...
Hello,
I am trying to simulate three inverters connected in sequence using cadence ams simulator
and a stimulus file that drives the input with a vpulse.
I cannot make it work. The input is not driven and stays at 0.3V with vdd at 1v. (All views are schematic)
I use the same stimulus file...
Hello,
I have the same unbound pin error during LVS.
The ...EXTRACT.rul has the code:
label( m1_text M1 )
. . .
label( m1_textt M1 )
. . .
m1_text = textToPin( "M1_CAD" type("TEXT") )
. . .
m1_textt = textToPin( "ME1" type("drawing") )
I have tried different combinations when I create the...
Hello,
Does anyone know if it is possible to use variable size of wire or pin names in cadence virtuoso schematic editor? (i.e. bus<0:maxLen>)
Thanks in advance,
Thodoros
Is Vdd enabled?
Hello,
I have noticed that in ic5 and even when I shipped to ic6 vdd of analog lib might not be enabled, as what it just does is getting noise from the input. (I am referring to the picture below).
So what I usually do is to use vdc instead of vdd. However this is not...
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