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Recent content by siddharthakala

  1. S

    Where can I buy FPGAs and CPLDs in India

    Where can I buy Xilinx FPGAs and CPLDs in India. I am looking forward to designing my own FPGA/CPLD boards but could not figure out where to buy FPGAs from in India. International websites like elements14 and AvnetExpress seem to be charging a lot for these chips. *****I am not looking to...
  2. S

    FIFO depth calculation....

    Thanks for the suggestion. Actually, I have read all the articles on FIFO by Cummings and know how FIFO work. The problem is none of the articles mention anything about depth calculation. I couldn't find a single article that thoroughly and clearly covers depth calculation. Not even and any of...
  3. S

    FIFO depth calculation....

    Please suggest some good article on FIFO depth calculation that explains it in detail. All the articles and papers I have found just either give a brief overview, provide very incomplete explanation in a page or two, or just explain how it could be designed using VHDL/Verilog. Please tell me...
  4. S

    Please suggest some good material on asynch FIFO and CDC

    Please suggest some good books or material that include topics such as asynchronous FIFO depth calculation, Clock Domain Crossing, etc. I have been spending most of my time going through a lot of material online, and some research papers including Sunburst papers on FIFOs and CDC, but none of...
  5. S

    Need some good material on DDR DRAM to design DDR2 memory controller

    Thanks a lot Shan. This seems quite helpful. I know about Xilinx'x MIG, but actually, I want to design my own controller, maybe just a very simple one, rather than using an IP core. Will share it as soon as I get done with it. :)
  6. S

    Need some good material on DDR DRAM to design DDR2 memory controller

    Hi, I need to design a DDR2 memory controller for Atlys board with Spartan-6 FPGA. I was wondering if someone could suggest some good learning material to understanding the working of DRAMs and memory controllers. I am not looking for memory controller codes but for their working so I could...
  7. S

    Writing synthesizable task in verilog

    Exactly... these are the rules that I follow for writing synthesizable code. And thats why I am confused about using tasks containing blocking assignments in sequential blocks. Doesn't this mix up blocking and non blocking assignments violating the above mentioned rules. Or, with the use of...
  8. S

    Writing synthesizable task in verilog

    But if I use blocking assignment inside a task and use that task in a sequential block (as in the example above), wouldnt it be inappropriate i.e. indirectly mixing blocking and non-blocking assignments.
  9. S

    Writing synthesizable task in verilog

    Can we use tasks (or functions) in sequential always blocks in synthesizable verilog code?? I couldnt find any proper set of guidelines or rules describing the use of tasks and functions for synthesis. I know we are not supposed to use timing control statements such as @, wait, #delay, etc...
  10. S

    Xilinx ISE with SystemVerilog

    I actually changed the code to remove all the warnings and didnt care about the SV warning at that time, and its been quite some time so I dont remember what it was. The Synplify tool that I have is specific for Lattice FPGAs only, maybe thats why I dont have SV support. Also, I have just used...
  11. S

    Xilinx ISE with SystemVerilog

    A few days back I got a warning on Xilinx ISE after synthesizing a design which said something like - Certain features are only available in SystemVerilog mode. Since then I have been trying to see how to activate this "SystemVerilog mode" but didnt get a clue about it. Does anyone know if there...
  12. S

    Need help regarding implementing UART on FPGA

    I need a little help with implementing and testing a UART that I have designed. I know to run the UART core on FPGA I will need to use HyperTerminal and then connect the FPGA through USB-UART of my Nexys3 FPGA to USB of my PC. But what I dont understand is which USB port on my PC I need to...
  13. S

    Want to install and use Fedora Electronic Lab (FEL)

    Hi, I want to install and use the Fedora Electronic Lab (FEL) but dont know how exactly to do that?? :( I am not a software expert and have no experience, whatsoever, with installing any kind of OS. I have never used any OS other than Windows. I have went through their installation...
  14. S

    Parameterized demultiplexer in verilog

    clogb2 function does not actually synthesize to any actual hardware. Its just a constant function used in order to calculate the complex parameterized values. During synthesis process, on of the very initial tasks the tool performs is code related processing, i.e. calculation of constants...
  15. S

    Parameterized demultiplexer in verilog

    Hi, I am trying to design a parameterized 1-to-N demultiplexer in Verilog but couldn't come up with proper code for it. I know how to design a dmux but am having trouble with making it parameterized. It would be great if someone could help me out with it. Thanks Sid
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