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Recent content by shyam4908

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    DDR3 Evaluation Board

    Hi , I am looking for FPGA evaluation board (prefereed with xilinx FPGA)....it should have DDR3 Interface...and cost to be withtin $100, If any one has reference boards...plese post -Shyam
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    RTL Compiler : create_clock command

    What is the problem with this. These are given in sdc file set PERIOD_HCLK 20 set HCLK_RISE 0 set HCLK_FALL [expr $PERIOD_HCLK*0.5] create_clock -period $PERIOD_HCLK -waveform {$HCLK_RISE $HCLK_FALL} "hclk" set_dont_touch_network "hclk" set_drive 0 "hclk" --- I am geting the in Compiler as...
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    [SOLVED] Help in multiplication using VHDL

    use ieee.std_logic_unsigned.all. If any other library..please let me know
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    [SOLVED] Help in multiplication using VHDL

    Library ieee; use ieee.std_logic_1164.all use ieee.std_logic_arith.all; entity mul is ( a : in std_logic_vector(15 downto 0); b : in std_logic_vector(15 downto 0); prd : out std_logic_vector(31 downto 0) ); architecture behav of mul is begin prd <= a * b; end -------------------- Use the...
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    Verilog to detect double rising edge

    module CS_Detect ( input clk, edges, output reg cs ); reg d_edges; wire pos_edge; reg pos_db_edge := '0' ; //Delay the edges signal always@(posedge clk) d_edges <= edges; //postive edge detection pos_edge = edges && !d_edges; neg_edge = !edges && d_edges; //number of posedge...
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    Help:problems with VHDL,wish someone help me solve it

    entity score is port( load :in std_logic; clk,up,dn,en1,en2:in std_logic; scorein :in std_logic_vector(3 downto 0); scoreout :out std_logic_vector(3 downto 0) ); end score; architecture behave of score is signal temp :std_logic_vector(3 downto 0); begin process(load,clk) begin temp...
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    MIG DDR2 controller virtex5

    Hi, Try to follow this 1. check wheter clk period of the model is within the range u r operating 2. Check whethet, the ddr2 model attached supports all the fetaures enabled in MIG 3. Check the initiationlation, in ddr2 model you should see init done indication 4. All the timing paramemter -shyam
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    FPGA Project Suggestion

    Hey, as a starter , u can always start with implementation of booth multipler..it is very easy..but at the same time gives you lot of info on the logic and coding exposure
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    IO Pad max frequency Calculation

    Hi, What are the parameter needs to be considered for calculating max frequency of IO pad in FPGA...Say for example IO pad with voltage 2.5V and drive strength of 16mA...I know that we need to used the DC switiching characterstic of the device..but not sure on parameter needs to be...
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    What is wrong with this Verilog code? Help! I am a newbie

    Re: What is wrong with this Verilog code? Help! I am a newbi I modified your code and is below module normalize ( input reset, input clk, input [7] img, //w.r.t u r code i am assuming these as 8bit input [7] m, //w.r.t u r code i am assuming these as 8bit input [7] v, //w.r.t u r...
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    How to generate the 30s delay, traffic light, vhdl code

    Re: How to generate delay? you need a set of counter to implement the timers... First up all u need to find the 1micro-second tick..the generation of this depends on the clock operating frequency of your circuit..for example if u r operation @ 200Mhz.. then u need to design a counter to...
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    What is wrong with this Verilog code? Help! I am a newbie

    Re: What is wrong with this Verilog code? Help! I am a newbi looking at the code i think u u missed "m" in the sensitivity list..let me know the exact problem
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    Input Duty Cycle in XILINX Virtex5 FPGA

    Thanks philoman... But the duty cycle correction works only for clk1x..i.e. clk0, clk90, clk270...but for clkfx it varies depend on M/D....i do not want to use one more dcm to generate clkfx using the output of first dcm..i want to know the tolerance for M/D values..
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    Input Duty Cycle in XILINX Virtex5 FPGA

    Hi, Can i convert the input clock with duty cycle 40/60 to nearly 50/50 duty cycle using DCM (or) PLL in xilinx Vitertex5 FPGA Regards Shyam
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