Input Duty Cycle in XILINX Virtex5 FPGA

[shyam4908]

Hi,

Can i convert the input clock with duty cycle 40/60 to nearly 50/50 duty cycle using DCM (or) PLL in xilinx Vitertex5 FPGA

Regards
Shyam

 

[philoman]

Well, you can set the DCM's DUTY_CYCLE_CORRECTION attribute to true.
Refer to Virtex-5's user guide ug190 and search 'duty cycle correction' for more details.

 

[shyam4908]

Thanks philoman...
But the duty cycle correction works only for clk1x..i.e. clk0, clk90, clk270...but for clkfx it varies depend on M/D....i do not want to use one more dcm to generate clkfx using the output of first dcm..i want to know the tolerance for M/D values..

 

[dilinx]

Hi shyam,
U can use PLL's "CLKOUT[0:5]_DUTY_CYCLE" attribute to get required (50%) duty cycle.