Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hello, I was running the example flat flow design for Tessent scan & ATPG tool. I got an error in the 4th stage (insert_scan) while running the set_system_mode analysis command. It says that at cycle 6, time 250, some pin should be 1, but it is simulated as X. I am attaching the screenshot. How...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
