Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to solve error in Tessent scan & ATPG

Status
Not open for further replies.

shuva

Newbie
Joined
Jun 24, 2021
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
17
Hello, I was running the example flat flow design for Tessent scan & ATPG tool. I got an error in the 4th stage (insert_scan) while running the set_system_mode analysis command. It says that at cycle 6, time 250, some pin should be 1, but it is simulated as X. I am attaching the screenshot. How can I solve this error? Thank you.
1_error_details.PNG
1.PNG
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top