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Recent content by shrbht

  1. S

    operation table in 0.18um smic

    what's mean of "su" "sd" in operation table of smic ? thank u
  2. S

    question about calibre lvs rules errors

    question about calibre when I write calibre lvs rule , there are perhaps errors for example DEVICE MN(n) nmos_rec poly(G) nsd(D) nsd(S) psub(B) how can I see the nmos_rec , nsd , poly and psub in layout if there are nmos which can not be extracted? thanks
  3. S

    Cdl out Issue - auto to do "save and check"

    Re: Cdl out Issue ? check hierachy in schematic
  4. S

    calibre star-rcxt flow support gate-level RC extraction?

    rc extraction in calibre calibre CCI--- star-rcxt flow support gate-level RC extraction? OR the flow only support transistor level RC extraction? thank u
  5. S

    how to timing closure using SOC encounter under 0.18um?

    encounter timing closure flow under 0.18um synopsys flow : PC + Astro cadence flow? thank u
  6. S

    Calibre mismatch problem.

    there are two problem of bad subtype and bad type layout schematic 1 RNPPO_MM_WELL RNPPO_MM 2 C(CNMOS) MN(N18_MM) I guess : 1 N+ POLY resistor is in nwell in layout , so named RNPPO_MM_WELL but in source its name RNPPO_MM...
  7. S

    wanted! ICC 200703 lab guide

    I need the lab guide of ICC 200703! thank u
  8. S

    wanted! ICC 200703 lab guide

    IC compiler 2007.03 lab guide ! thank u in advance
  9. S

    calibre xRC help! - pex_fmt_source_based_flow

    pex_fmt_source_based_flow I use calibre 2006.3 when LVS is clean , I extract gate level R+C to generate SPEF . setenv PEX_FMT_SOURCE_BASED_FLOW ON in .cshrc but in FMT step : warning bad source pin map 3 HP :X3/X123:ZN I search X3 in layout netlist , it is ICV_* cell. how to solve this...
  10. S

    help about calibre-star-rcxt flow!

    help about calibre-star-rcxt flow! Is there any detail reference ? calibre lvs generate CCI (gate-level) calibre query [svdb] then ....
  11. S

    request for calibre rule writing student guide

    calibre rule writing & ( guide | explanation) thanks in advance
  12. S

    help! about design rule!

    in tsmc 0.35um logic design rule why need this rule? what's mean? thanks in advance!
  13. S

    what tools for transistor level timing analysis?

    transistor level timing analysis what tools for transistor level timing analysis? thanks!
  14. S

    How to add decap cell in Astro?

    How to add decap cell in Astro? Thanks in advance
  15. S

    Need of Endcaps in design?

    It's for latch up ! perhaps
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