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Hi,
SETUP analysis:
The STA tool is used to ensure that the data arriving at the flop input is not arriving in the setup window.
In order to ensure it, the STA tool checks that (Arrival time) < (MAX_DELAY – Tsetup)
HOLD analysis:
The STA tool is used to ensure that the data arriving at the...
Hi,
Cut on lower left corner : R0 orientation
Cut on lower right corner: R90 orientation
Cut on upper right corner: R180 orientation
Cut on upper left corner: R270 orientation
Similarly You can have
MX90
MY180
.
.
.
Etc:
Where M represents Mirror an X,Y represents the axis
thanks,
Shobhit
OCV: On chip Variation of Voltage, temperature, Process.
When a chip is fabricated, it is present with other identical chips on the wafer. There are some variations which happen on the complete wafer, these are referred to as global variations, and the variations which happen on the chip only...
1) Set the following root attribute to TRUE
attribute ==> remove_assigns
2) instruct RTL compiler which buffer to use , using the blow command
set_remove_assign_options -buffer_or_inverter <BUFFER LIBCELL NAME>
3) run incremental optimization.
synth -to_mapped -incr
--
Shobhit
Hi,
Min cut violation is a DFM requirement. It constrains physical designer to have a minimum density of vias. The reason for this requirement is that due to etching vias may get etched away.
FIX: replace the single cut via with multi cut vias. The issue will get resolved.
Ideally setup and hold violation should not be present on same timing path (F2F path).
(BUT THERE CAN BE SITUATION WHERE BOTH SETUP slack & HOLD slack are negative)
But if such a situation happens we will never be able to fix these violations and the design will fail.
The reason is that when...
Hi,
A Flip Flop is made up of master latch and a slave latch.
Setup Time: We need to provide enough time for the input capacitance of Master latch to be charged up or discharged down, before the Master latch captures the data. To ensure that this happens ,we have a setup time requirement. If...
Hi dll_fpga,
I dont think that you will be able to design such a circuit w/o sequential elements.
The reason is that you need to save the counts (a memory mechanism) and thus you need an FSM.
You cannot do away with the counter which is a sequential circuit.
Yes you can remove the divider if...
Hi Suman,
Sometimes the pin names are misleading.
Just open up the RAM lib and then check for the clock attribute of CLKA pin.
If its not there, then it is a data pin.
regards,
Shobhit
Hi,
I have drawn the diagram for the circuit. The diagram is self explanatory. The salient points are.
1) minimum 3 bit counter is required to count 5 bit stream. there are separate counters for counting '0' & '1'
2) The counters are -ve edge triggered ripple counters
3) The data stream must...
Hi,
It is not necessary that the power pads & the ground pads are same on a chip.....
After the power is laid down after floorplan, we run IR drop analysis on the power as well as ground and a check is made on
1) How much a VDD is possible to fall at the power pins of a hard macro/ memory
2)...
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