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Hello all!
I am using gpdk180nm CMOS lib for designing BGR circuit. I have designed the circuit using current mirror. But to improve this circuit I am using op-amp. I need to know what type of op-amp should I use for getting 1.12 V const ref voltage for temp range -40 to 125?
What should be...
for gpdk180nm uncox=400u and upcox=70u
Vtn= 470mV and Vtp=450mv
Please guide me through calculations for how to design of 2 stage opamp with specs as
Vdd=1.8V, Cc=800fF, Gain = 50-60dB?
I have tuned the circuit. I obtained all transistors in saturation region. Now i am faciing one problem.
Gain is coming out to be 52dB and UGB is only 6.7Mhz.
It should be atleast 20MHz and >70dB
How to approach for that?
here i have designed nmos input folded cascode transistor. problem is that the pmos transistors and last two nmos tx in cascode structure are working in region 2 i.e triode region. also for biasing i have set v3 and v4 as 880mv and 770mv.
Suggest me some changes for making all transistor...
Yes I consulted textbook Behzad Razavi also. I am designing the circuit for small powered devices in cadence gpdk180. I want to know the optimal assumptions for the circuit.
I assumed the design parameters as
1) Vdd = 1.8V
2) Power = 54uW (I comes out to be 30u)
3) SR = 10V/usec
4) Load cap =...
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