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xilinxcorelib modelsim
Thanx for this information.....but can I get a step by step instruction on how to simulate my single port ROM generated through core generator???.....Its really getting messed up for me...
modelsim xe
hi...
I am using ISE 10.1 to build a single port rOm using IP core generator. And using Modelsim for simulation . how do I compile the unisim, simprim , xilinx core libraries (these libraries reside in the following place of my system : F:\xilinx\10.1\ISE\vhdl)....I am writing...
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